| http://www.w3.org/ns/prov#value | - The present invention is a system and method for completing a read transaction between an initiator device and a host memory device in a computer system, wherein the target latency for the read transaction (that is, the time from the beginning of the read transaction until the data are present in the bus bridge device's data FIFOs) is dynamically measured and used to optimize the retry behavior of
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