| http://www.w3.org/ns/prov#value | - The memory device according to claim 1, wherein the bit lines are grouped into at least one sub-set and the means for biasing includes a biasing structure for each sub-set, the biasing structure including means for discharging the corresponding bit lines and means for enabling the means for discharging when an indication of a voltage on the corresponding deselected bit lines reaches a threshold va
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