| http://www.w3.org/ns/prov#value | - This one-shot pulse generating circuit 126 includes an AND circuit 128 which receives an input signal I and a signal corresponding to the input signal I delayed by a delay circuit made up by an odd-number stage of inverters 127 1 to 127 2n+1, where n is a positive integer, and outputs a one-shot pulse having a pulse width equal to the delay time of the delay circuit and having the rising edge sync
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