| http://www.w3.org/ns/prov#value | - A logic gate clamping circuit comprising:a logic gate, the logic gate including an input for receiving an input signal, an output, and a clamping node, the logic gate being coupled to a ground potential; and bias means coupled in a feedback relationship between the output of the logic gate and the clamping node for increasing the speed of the transitions of the input signal at the output and for m
|
