| http://www.w3.org/ns/prov#value | - A logic gate clamping circuit comprising:a logic gate, the logic gate including an input for receiving an input signal, an output, and a clamping node, the logic gate being coupled to a ground potential; bias means coupled to the clamping node for increasing the speed of the transitions of the input signal at the output and for minimizing power consumption of the logic gate the bias means further
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