| http://www.w3.org/ns/prov#value | - line provided on said first MOS transistor, said first bit line crossing said first word line; anda second memory cell stacked above said first memory cell through an interlevel insulator, said second memory cell including a second bit line provided on said interlevel insulator, a second word line disposed above said interlevel insulator soas to cross said second bit line, a second MOS transistor
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