| http://www.w3.org/ns/prov#value | - The state shown in FIG. 4 is an example in which the lock occurs at the 1.5 periods, the rising position of the delay output T8 in the 8th stage is located at the back of the rising position of the delay output T25, and the rising position of the delay output T9 in the 9th stage is located in front of the rising position of the delay output T25.
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