| http://www.w3.org/ns/prov#value | - umn (bit line) lying within the memory cell array 123, a command decoder 102 for generating internal control signals in response to control signals such as a chip select signal /CS, etc. inputted from outside, an output buffer 120 for outputting data read from the memory cell array 123 to the outside, an output register 118 for controlling timing provided to send data to the output buffer 120 acco
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