| http://www.w3.org/ns/prov#value | - Further, in the case of write or read data after removing a block having an imperfect memory cell, if the state of the except portion is established by the information read out from the control information registration portion 4 before the data is established, no time lag is introduced in operation by the provision of such additional circuits as the switch matrix and so forth, and real-time operat
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