| http://www.w3.org/ns/prov#value | - During processing of an auxiliary processing instruction in which operands are in the form of a series of vector elements, the source 1 register identifier generator 62 generates the SRC 1 REG ID source 1 register identifier signals using a plurality of diverse addressing modes, including a register stride mode and a register indirect mode, both of which are similar to the memory stride and memory
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