| http://www.w3.org/ns/prov#value | - Finally, during step 632, a thick oxide interlayer dielectric is deposited and planarized and processed to form contact holes, a cell capacitor, e.g. 116 FIG. 2, connects between one of a source and drain region and a digit line, between the ferroelectric capacitor and a wordline, and wiring levels, as in conventional DRAM processing.
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