About: http://webisa.webdatacommons.org/336495543

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	As illustrated in FIG. 6, when INPUT is a logic LOW, OUTPUT is also LOW (e.g., OUTPUT=GND), such that FET1 is not conducting while FET2 is conducting, and therefore VGD of FET1 and VGS of FET2 are both positive.
http://www.w3.org/ns/prov#wasQuotedFrom	google.com