| http://www.w3.org/ns/prov#value | - eby select a column (bit line) lying within each of the memory cell arrays 200A through 200D, a control logic 209 which generates internal control signals in response to control signals such as a chip select signal /CS, etc. inputted from outside, a data output buffer 211 which outputs data read from the memory cell arrays 200A through 200D to the outside, an output buffer 215 which provides a dat
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