| http://www.w3.org/ns/prov#value | - emories having longer address and data bus delays than the other and thereby requiring more access cycles; means for reconfiguring the cache memories without invalidating or transferring data, including means for adding an increment to or subtracting an increment from one of said caches to increase or decrease the size and associativity thereof by the incremental size and associativity, and to cha
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