| http://www.w3.org/ns/prov#value | - In response to a signal Not .0.-1, FET's 36 and 37 in bit partitioning circuit hold down both the true and complement column lines 1-A and Not 1-A. From the description of the operation of the array, it can be seen that no FET in the .0.-1 section of the AND array can be turned on except at .0.-1 time when the signal Not .0.-1 is down.
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