PropertyValue
http://www.w3.org/1999/02/22-rdf-syntax-ns#type
http://www.w3.org/ns/prov#value
  • During the synthesis process, simulator and other tools (step 62) verify that the circuit and interconnect systems described by the netlist model will meet logic and timing specifications.
http://www.w3.org/ns/prov#wasQuotedFrom
  • google.com