About: http://webisa.webdatacommons.org/371591845

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIG. 12 is a timing chart explaining the operation of a reset circuit in the case where clock output is suppressed until the RF part supplying a clock becomes stable in oscillation;
http://www.w3.org/ns/prov#wasQuotedFrom	google.com