About: http://webisa.webdatacommons.org/372092399

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIGS. 6A and 6B are a timing diagram and a schematic diagram, respectively, of an SXGA row addressing circuit, enabling a resetting pulse to one row during a row period, eight rows prior to writing; and
http://www.w3.org/ns/prov#wasQuotedFrom	google.co.uk