| http://www.w3.org/ns/prov#value | - FIG. 4B is a timing diagram of a number of input signals applied to the gate driver circuit of FIG. 4A. FIG. 4C is a timing diagram of a number of the output signals generated by the gate driver circuit of FIG. 4A. FIG. 5 is a simplified high level block diagram of a flat panel being tested using a multitude of shorting bars, in accordance with one embodiment of the present invention.
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