| http://www.w3.org/ns/prov#value | - FIG. 2A is a circuit diagram showing a basic configuration of a CMOS inverter circuit, and FIG. 2B is a timing chart of the CMOS circuit of FIG. 2A. A plurality of inverters, each of which is configured as shown in FIG. 2A, are connected in series in the serial delay circuit 10 and the logic circuit 13.
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