| http://www.w3.org/ns/prov#value | - ; (h) bus master means in the first processor fori. determining if the request is a read request or a write request, ii. examining the status bits in a first location of the cache of the first processor corresponding to the first address, iii. generating a first cache miss signal if the Valid bit is a 0 or if the request is a write request and the Valid bit is a 1 and the Exclusive bit is a 0
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