| http://www.w3.org/ns/prov#value | - a x18b4 operation of the semiconductor memory device of FIGS. 7 and 8; FIGS. 13 and 14A through 14D are diagrams for explaining a x9b4 operation of the semiconductor memory device of FIGS. 7 and 8; FIG. 15A is a cross-sectional view of a semiconductor package into which the semiconductor memory device of FIG. 6 is mounted; FIG. 15B is a plan view of the semiconductor memory device of FIG. 15A; FIG
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