| http://www.w3.org/ns/prov#value | - Each of these processors have access to a common memory 130 which stores a timer expiration stack, Layer 3 addresses served by this node, a map of DSL number to Layer 3 addresses, program, and working areas for: TEI management, DSL numbers, CES, Layer 2 active frame state, variables, counters, buffers for Tx and Rx, Layer 3 active call states and other information which is commonly shared among th
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