| http://www.w3.org/ns/prov#value | - FIG. 2a is a schematic diagram of a first embodiment of a neural processor in FIG. 1 comprising N rows of N dimensional CCD registers for implementing a synaptic interconnection matrix SYNP self-connected (recirculating) in the rows for storing a matrix T loaded prior to the operation of the system, a column of N multipliers MUL with a common multiplier input to each, a column of N registers ACCUM
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