| http://www.w3.org/ns/prov#value | - FIGS. 8A and 8B are a cross-sectional view and the equivalent circuit diagram of a memory cell formed using a self-aligned stacked gate memory transistor where the source of the memory transistor is merged directly with the base of a PNP IGBT. FIGS. 9A and 9B are a cross-sectional view and the equivalent circuit diagram of a memory cell formed using a self-aligned stacked gate cell and a select tr
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