| http://www.w3.org/ns/prov#value | - ayer of dielectric with high dielectric constant on said side wall and said bottom wall of said gate opening; D. depositing amorphous gate electrode material into said gate opening to fill said gate opening after said step C; E. doping said amorphous gate electrode material in said gate opening with an N-type dopant using a low energy implantation process when said field effect transistor is an N-
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