| http://www.w3.org/ns/prov#value | - FIG. 3 is a flow chart representing exemplary processing steps for fabricating the array of charge trapping dielectric memory cells of FIG. 2 a; FIGS. 4 a-4 k represent cross section views of a portion of the array of charge trapping dielectric memory cells of FIG. 2 a at selected processing steps during fabrication; and
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