| http://www.w3.org/ns/prov#value | - Another approach for the entry into test mode using such a dedicated terminal is disclosed in Shimada et al., A 46-ns 1-Mbit CMOS SRAM, IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, (Feb. 1988) pp. 53-58, where a test mode is enabled by the application of a high voltage to a dedicated control pad while performing a write operation.
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