| http://www.w3.org/ns/prov#value | - A dynamic random access memory device (DRAM) of claim 8, wherein said common word bus line comprises:N pairs of a first block selection line and a second block selection line corresponding to each column of said array, wherein N is an integer; and N pairs of a first switching means and a second switching means, wherein each of said word lines located on said row of said array is selectively connec
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