| http://www.w3.org/ns/prov#value | - What are shown as IV1, IV2 and IV3 are inverters to invert signals obtained corresponding to ON, OFF of switches 38, 36 and 39 respectively, and NA1 is a NAND gate to receive an output of the inverter IV1 and a signal obtained at a connecting point between the power source switch 36 and the resistor R2.
|
