| http://www.w3.org/ns/prov#value | - A memory comprising: a number of transistors, each transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a body region in a substrate between a source region and a drain region, the dielectric layer including a hafnium oxide layer in contact with a lanthanide oxide layer, the hafnium oxide layer structured as one or more monolayers of hafnium oxide; and a numb
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