| http://www.w3.org/ns/prov#value | - 20140298142MEMORY CONTROLLER, SEMICONDUCTOR MEMORY APPARATUS AND DECODING METHOD - A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold d
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