| http://www.w3.org/ns/prov#value | - A memory comprising: a number of access transistors, each access transistor including a gate coupled to a dielectric layer, the dielectric layer disposed on a body region in a substrate, the body region between a source region and a drain region; and a number of bit lines, each bit line coupled to one of the number of access transistors, wherein the dielectric layer includes a hafnium oxide/lantha
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