| http://www.w3.org/ns/prov#value | - FIG. 11 is a graph of simulated flat band voltage versus erase bias time for a cell like that described with respect to FIG. 10, assuming a dielectric constant of 5, but with various electron barrier heights ranging from 3 eV to 4 eV. Under the same bias voltage of negative 18 V, cells having a higher barrier height provide better suppression of erase saturation.
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