| http://www.w3.org/ns/prov#value | - FIG. 9 is a diagram illustrating operations involved in using the p-channel metal-oxide-semiconductor latch-up prevention circuitry of FIG. 6 in preventing latch-up in body-biased p-channel metal-oxide-semiconductor transistors on an integrated circuit such as a programmable logic device integrated circuit in accordance with the present invention.
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