| http://www.w3.org/ns/prov#value | - In other words, when there are a plurality of write requests to overlapping addresses between the above-described time T1 and time T2, only the write data based on the newest write request remains on the cache 400 and is managed as the generated differential set in the control unit 200 of the memory device A100 with respect to the range with the overlapping addresses.
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