| http://www.w3.org/ns/prov#value | - In the alternative, any combination of non- volatile memories may be reset using available device-specific reset commands. [0034] Architectures other than the shared chip enable and data command bus structure shown in Figure 1 may also limit the ability of the controller 144 to select which of the non- volatile memories 160 - 196 may simultaneously act in response to a command such as reset.
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