| http://www.w3.org/ns/prov#value | - FIG. 2A is a block diagram illustrating an embodiment of resampler 108A in communications devices 10A and 10C. Resampler 108A includes a variable fractional delay (VFD) filter 202A and a frequency locked loop 204A. Frequency locked loop 204A includes a frequency discriminator 212A, a loop filter 214, a fractional delay numerically controlled oscillator (NCO) 216, and a read control unit 218.
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