| http://www.w3.org/ns/prov#value | - If, however, the enable signal is not 1 or is switched to 0, then DZB remains precharged, and the clock signal is gated (i.e. the clock signal does not rise to 1), and the output of the latch 104 remains constant.For example, the precharge stage may begin when the enable signal and/or the test enable signal is set to a logical 1 and the clock signal is at a logical 0.
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