| http://www.w3.org/ns/prov#value | - The parallel encoder of claim 1 wherein:said byte adder circuitry includes a plurality of byte adders arranged in m byte-additive stages where m is the lowest integer satisfying the relationship 2m ???K, with each of the byte adders in a first of said byte-additive stages receiving two of said intermediate product bytes and providing a single byte output to a byte adder of a subsequent stage. 6.
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