| http://www.w3.org/ns/prov#value | - Designers have gotten better at these things now and the area budgets for these types of things have gotten in the affordable range as transistors have gotten smaller.FWIW, In a pipeline design (like a cpu), sometimes it is advantagous to have a clock-follows-signal clocking topology or even an async strategy instead of a clock tree, but there of course is a complication if there is a loop or cycle
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