| http://www.w3.org/ns/prov#value | - The high-level period of the control pulse shown in FIG. 2(C) corresponds to the period in which the 96-bit digital data is read out from the shift register 23, and is a period in which the 96-bit digital data consisting of the two kinds of error correcting codes and the 4-channel information data within the digital signal e which is obtained from the exclusive-OR circuit 44.
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