About: http://webisa.webdatacommons.org/448672018

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIG. 2 is a circuit schematic of a multiplier circuit including an eight transistor gain cell incorporating the preferred embodiment of the present invention, and
http://www.w3.org/ns/prov#wasQuotedFrom	google.com