| http://www.w3.org/ns/prov#value | - The circuit of FIG. 5 is operated to perform the steps described with respect to FIGS. 4A-4D. The data register 43 include two rows of individual latches, one row including latches 71, 73, 75 and 77, and the other row including latches 79, 81, 83 and 85.
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