| http://www.w3.org/ns/prov#value | - FIG. 5A and 5B show a schematic circuit diagram of a memory interface mechanism of FIG. 4; specifically, FIG. 5A is a schematic circuit diagram of a receive (rx) path portion for receiving source data from a source port, and FIG. 5B is a schematic circuit diagram of a transmit (tx) path portion for transmitting destination data to a destination port;
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