| http://www.w3.org/ns/prov#value | - As shown in FIG. 28, however, a buffer circuit 300 for the formation of an input waveform, in some cases, exists between terminal DQM of module substrate 102 and terminal DQM (chip) of a single chip 117 that becomes the test object. [0029] In addition, control signals and address signals except for control signals inputted/outputted using data input/output terminals DQ
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