| http://www.w3.org/ns/prov#value | - The multi-threaded memory of claim 4, wherein the memory includes:at least N decoders sufficient in number to ensure a ratio of at least one said decoder per storage element; the write interface, for each storage element, including one port per said at least one decoder for operatively connecting the storage element to the decoder such that plural threads can be written to simultaneously. 6.
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