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About: http://webisa.webdatacommons.org/58010467

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http://www.w3.org/1999/02/22-rdf-syntax-ns#type
http://www.w3.org/ns/prov#value
  • FIG. 2A is a circuit diagram of a two input NAND logic gate implemented using three dual gate FET devices 501, 504, and 505.
http://www.w3.org/ns/prov#wasQuotedFrom
  • google.com