About: http://webisa.webdatacommons.org/64416271

Property	Value
http://www.w3.org/1999/02/22-rdf-syntax-ns#type	http://www.w3.org/ns/prov#Entity
http://www.w3.org/ns/prov#value	FIG. 1B is a circuit diagram illustrative of a first delay circuit provided in a conventional clock generator circuit having a phase lock loop of FIG. 1A.
http://www.w3.org/ns/prov#wasQuotedFrom	google.fr