| http://www.w3.org/ns/prov#value | - FIG. 3 is a plan view showing the first embodiment of an semiconductor package according to the present invention, FIG. 4 is a sectional view taken along line 4--4 of FIG. 3, and FIGS. 5 and 6 are sectional views showing the semiconductor package shown in FIG. 3 stacked and mounted on a substrate.
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